A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (poly or polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor and localize the source and drain dopants relative to the gate conductor.
Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform when using high mobility MOS transistors. One way to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress in the channel.
A compressive strained channel has significant hole mobility enhancement over conventional devices. A tensile strained channel achieves significant electron mobility enhancement. The most common method of introducing strain in a silicon channel region is to recess the source and drain regions adjacent to the channel and to fill the recessed regions with a stressor material by selective epitaxial growth.
A compressive strain in the channel is obtained when the stressor material epitaxially grown is SiGe. Similarly, tensile strain in the channel is obtained when the stressor material is Si:C.
SRAM devices, for example, use a mixture of such MOS transistors on an integrated circuit chip including carefully tailored and matched transistors utilized in the memory array (core region) as well as general purpose logic transistors used in various peripheral control circuits (logic region) which control access to the array. However, advanced SRAM devices have a tendency to produce various defects associated with selective epitaxial growth in moat tip regions. These defects are due to the reduced dimensions of the region, preventing proper epitaxial growth and resulting in extremely thin epitaxial layers. Such defects also result in degraded electrical characteristics, degraded contacts and silicide formation, and poor diode characteristics. In addition, transistors fabricated with selective epitaxial regions in the source/drains suffer from high off-state current due to subsurface leakage.
It would be advantageous to have an SRAM device and method that effectively and reliably provides strain to the device in order to improve carrier mobility, while reducing defects associated with selective epitaxial growth in moat tip regions of the core region.